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Standard ICs
LCD segment driver
BU9706KS
The BU9706KS is a 40-output LCD segment driver provided with a 40-bit shift register and a 40-bit latch. As the 40-bit shift register can be divided into two 20-bit sections, it can be used efficiently, based on the number of segments and the character configuration. Also, by using a number of BU9706KS drivers, it is possible to configure an LCD segment driver of more than 80 bits. As the liquid crystal drive voltage can be set externally to any value, it can be used as a driver IC for both static and dynamic drive in various types of liquid crystal display panels.
*Featuresshift register and 40-bit latch enable serial 1) 40-bit
input - parallel output. 2) Shift register can be divided into two 20-bit sections. 3) Power supply voltage: 3.5 to 6V. 4) LCD drive voltage: 3 to 6V.
5) Can accommodates duty of 1 / 8 to 1 / 16. 6) Can be used as a driver IC for static drive by setting the liquid crystal drive voltage externally (V3 = VDD, V2 = V5 = VSS, connect DF as LCD common).
*Block diagram
O1 41 O2 40 O3 39 O38 O39 O40 4 3 2
VDD 49 V2 43 V3 44 V5 45 DF 51
40 bit Latch LCD Dr
40
LOAD 47 20 DII 53 CP 48 VSS 42 D
20 bit SHIFT REGISTER
20 D
20-bit SHIFT REGISTER
1
DO40
CK
CK
54
55
DO20 DI21
1
Standard ICs
BU9706KS
*Absolute maximum ratings (Ta = 25C, VSS = 0V)
Parameter Power supply voltage LCD power supply voltage Input voltage Power dissipation Operating temperature Storage temperature Symbol VDD VDD - V5 VIN Pd Topr Tstg Limits - 0.3 ~ + 6.5 0 ~ + 6.5 VSS - 0.3 ~ VDD + 0.3 500 - 20 ~ + 70 - 55 ~ + 125
V3 > V5 VSS.
Unit V V V mW C C
The LCD power supply voltage must satisfy the condition of VDD > V2
*Recommended operating conditions (Ta = 25C, VSS = 0V)
Parameter Power supply voltage LCD power supply voltage Input voltage Symbol VDD VDD - V5 VIN Min. 3.5 3.0 0 Typ. -- -- --
V3 > V5 VSS.
Max. 6.0 6.0 VDD
Unit V V V
The LCD power supply voltage must satisfy the condition of VDD > V2
VSS O1
O10
O11
O12
42 41 40 39 38 37 36 35 34 33 32 31 30 29 V2 V3 V5 N.C. LOAD CP VDD N.C. DF N.C. DI1 DO20 DI21 N.C. 43 44 45 46 47 48 49 50 51 52 53 54 55 56 1 2 3 O39 45 O38 O37 6 O36 78 O35 O34 9 10 11 12 13 14 O33 O32 O31 O30 O29 O28 28 27 26 25 24 23 O14 O15 O16 O17 O18 O19 O20 O21 O22 O23 O24 O25 O26 O27
O13 22 21 20 19 18 17 16 15
*Pin assignments
O2 O3 O4 O5 O6 O7 O8 O9
BU9706KS
2
DO40 O40
Standard ICs
BU9706KS
*Pin descriptions
Pin No. 2 ~ 41 43 ~ 45 49 42 53 Pin name O40 ~ O1 V2 ~ V5 VDD VSS DI1 I/O O -- -- -- I Function Output pin for the liquid crystal driver. VDD, V2, V3 or V5 is output depending on the latch content and the DF signal. Refer to the truth table for the output level. Power supply pin for liquid crystal drive Logic power supply pin and liquid crystal drive power supply pin Logic power supply pin Data input pin for the shift register (1 to 20 bits). Data is read to the first bit of the shift register at the clock signal falling edge. Data output pin for the shift register (1 to 20 bits). Data is output in synchronization with the clock signal falling edge. A 40-bit shift register is accomplished by connecting pins 54 and 55. Data input pin for the shift register (21 to 40 bits). Data is read to the 21st bit of the shift register at the clock signal falling edge. Data output pin for the shift register (21 to 40 bits). Data is output in synchronization with the clock signal falling edge. It is used to configure an LCD driver with more than 40 bits by connecting it to the DI pin of the BU9706KS at the next stage. Clock signal input pin for the shift register. The contents of the shift register are shifted by 1 bit only at the clock signal falling edge. Latch signal input pin for the 40-bit latch. The contents of the shift register are transferred to O1 to O40 at LOAD = "H" and the data is latched at LOAD = "L". While LOAD = "L", the latched data is held even if the contents of the shift register change. Input pin for the signal which produces AC for LCD drive.
54
DO20
O
55
DI21
I
1
DO40
O
48
CP
I
47 51
LOAD DF
I I
*LCD drive output pin truth table
Latch data H H L L DF H L H L On terminal voltage V5 VDD V3 V2
*Timing chart
CP DI1
40
1
2
3
39
40
1
2
O1 Load
O40
O39
O38
O2
O1 Load
O40
O39
LOAD
DF
* Shifted at CP input falling. * When the LOAD input state becomes "H", the contents of the shift register are transferred to the segment outputs O1 to O40, and when it is "L", the data is latched.
Fig.1
3
Standard ICs
BU9706KS
*Electrical characteristics (unless otherwise noted, Ta = 25C, VDD = 5 V) DC characteristics
Parameter Input high level voltage1 Input low level voltage1 Input high level current1 Input low level current1 Output high level voltage2 Output low level voltage2 ON resistance34 Current dissipation Symbol VIH VIL IIH IIL VOH VOL RON IDD Min. 4.0 -- -- -- 4.2 -- -- -- Typ. -- -- -- -- -- -- -- -- Max. -- 1.0 1 -1 -- 0.4 5 0.5 Unit V V A A V V k mA VIH = VDD VIL = 0V IO = - 40A IO = 0.4mA | VIN - VO |5 = 0.25V CP = DC No load Conditions -- --
1 Applied to DF, LOAD, CP, DI1 and DI21 pins 2 Applied to DO20 and DO40 pins 3 Applied to O1 to O40 pins
4 VDD = 5V, V2 = 2 / 3 VDD, V3 = 1 / 3 VDD, V5 = 0V 5 VIN = VDD, V2, V3, V5, Vo = On pin voltage
AC characteristics
Parameter Propagation delay time 1 Propagation delay time 2 Propagation delay time 3 DI CP setup time CP DI hold time CP pulse width Load pulse width CP load time LOAD CP time Maximum clock frequency
Not designed for radiation resistance.
Symbol tpLH, tpHL tp (L) tp (D) tsLH, tsHL thLH, thHL tw (CP) tw (L) tCL tLC fCP
Min. -- -- -- 50 50 125 125 250 0 3.3
Typ. -- -- -- -- -- -- -- -- -- --
Max. 250 250 250 -- -- -- -- -- -- --
Unit ns ns ns ns ns ns ns ns ns MHz DUTY = 50%
Conditions CP DOn delay time Load On delay time DF On delay time -- -- -- -- -- --
VDD = 5V, V2 = 2 / 3VDD, V3 = 1 / 3VDD, V5 = 0V
4
Standard ICs
BU9706KS
tw (CP) CP 0.8VDD 0.8VDD
tw (CP) 0.8VDD 0.2VDD 0.2VDD thLH thHL 0.8VDD 0.2VDD tpLH tpHL
tsLH tsHL DI1, DI21
DO20, DO40
0.8VDD 0.2VDD tCL tLC 0.2VDD
LOAD
0.8VDD 0.8VDD tW (L)
O1 ~ O40 tp (L)

DF
0.8VDD tp (D)
0.2VDD tp (D)
O1 ~ O40

tp
(L)
and tp (D) are times required before the O1 to O40 output amplitude becomes 80% and 20% respectively.
Fig.2 AC characteristics waveform
*Application example
COM1 LCD panel (16 commons, 120 segments) COM16 SEG1 SEG40 D Controller
O1 DI1 DO20 DI21
O40 DO40 BU9706KS
O1 DI1 DO20 DI21
O40 DO40 BU9706KS R LOAD
VDD
LOAD
CP
CP
DF
DF
V2
V3 V5
V2
V1 V2 V3 V4 V5 M CL1 CL2
V3 V5
R R R
R
Fig.3
5
Standard ICs
BU9706KS
*External dimensions (Units: mm)
12.4 0.3 10.0 0.2 42 12.4 0.3 10.0 0.2 43 29 28 0.5 0.15 0.1 0.15
56 1
15 14
2.15 0.1
0.05
0.65
0.3 0.1
SQFP56
6

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